On Sat, May 18, 2019 at 11:25:21AM -0300, Claudio Carvalho wrote: > From: Ram Pai <linuxram@xxxxxxxxxx> > > When the ultravisor firmware is available, it takes control over the > LDBAR register. In this case, thread-imc updates and save/restore > operations on the LDBAR register are handled by ultravisor. > > Signed-off-by: Ram Pai <linuxram@xxxxxxxxxx> > [Restrict LDBAR access in assembly code and some in C, update the commit > message] > Signed-off-by: Claudio Carvalho <cclaudio@xxxxxxxxxxxxx> Some of the places that you are patching below are explicitly only executed on POWER8, which can't have an ultravisor, and therefore the change isn't needed: > --- > arch/powerpc/kvm/book3s_hv.c | 4 +- > arch/powerpc/kvm/book3s_hv_rmhandlers.S | 2 + > arch/powerpc/perf/imc-pmu.c | 64 ++++++++++++-------- > arch/powerpc/platforms/powernv/idle.c | 6 +- > arch/powerpc/platforms/powernv/subcore-asm.S | 4 ++ > 5 files changed, 52 insertions(+), 28 deletions(-) > > diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c > index 0fab0a201027..81f35f955d16 100644 > --- a/arch/powerpc/kvm/book3s_hv.c > +++ b/arch/powerpc/kvm/book3s_hv.c > @@ -75,6 +75,7 @@ > #include <asm/xics.h> > #include <asm/xive.h> > #include <asm/hw_breakpoint.h> > +#include <asm/firmware.h> > > #include "book3s.h" > > @@ -3117,7 +3118,8 @@ static noinline void kvmppc_run_core(struct kvmppc_vcore *vc) > subcore_size = MAX_SMT_THREADS / split; > split_info.rpr = mfspr(SPRN_RPR); > split_info.pmmar = mfspr(SPRN_PMMAR); > - split_info.ldbar = mfspr(SPRN_LDBAR); > + if (!firmware_has_feature(FW_FEATURE_ULTRAVISOR)) > + split_info.ldbar = mfspr(SPRN_LDBAR); This is inside an if (is_power8) statement. > diff --git a/arch/powerpc/platforms/powernv/subcore-asm.S b/arch/powerpc/platforms/powernv/subcore-asm.S > index 39bb24aa8f34..e4383fa5e150 100644 > --- a/arch/powerpc/platforms/powernv/subcore-asm.S > +++ b/arch/powerpc/platforms/powernv/subcore-asm.S > @@ -44,7 +44,9 @@ _GLOBAL(split_core_secondary_loop) > > real_mode: > /* Grab values from unsplit SPRs */ > +BEGIN_FW_FTR_SECTION > mfspr r6, SPRN_LDBAR > +END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ULTRAVISOR) > mfspr r7, SPRN_PMMAR > mfspr r8, SPRN_PMCR > mfspr r9, SPRN_RPR > @@ -77,7 +79,9 @@ real_mode: > mtspr SPRN_HDEC, r4 > > /* Restore SPR values now we are split */ > +BEGIN_FW_FTR_SECTION > mtspr SPRN_LDBAR, r6 > +END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ULTRAVISOR) Only POWER8 supports split-core mode, so we can only get here on POWER8. Paul.
