From: Paul Mackerras <paulus@xxxxxxxxxx> - Pass SRR1 in r11 for UV_RETURN because SRR0 and SRR1 get set by the sc 2 instruction. (Note r3 - r10 potentially have hcall return values in them.) - Fix kvmppc_msr_interrupt to preserve the MSR_S bit. Signed-off-by: Paul Mackerras <paulus@xxxxxxxxxx> Signed-off-by: Claudio Carvalho <cclaudio@xxxxxxxxxxxxx> --- arch/powerpc/kvm/book3s_hv_rmhandlers.S | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S index d89efa0783a2..1b44c85956b9 100644 --- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S +++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S @@ -1160,6 +1160,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) ret_to_ultra: lwz r6, VCPU_CR(r4) mtcr r6 + mfspr r11, SPRN_SRR1 LOAD_REG_IMMEDIATE(r0, UV_RETURN) ld r7, VCPU_GPR(R7)(r4) ld r6, VCPU_GPR(R6)(r4) @@ -3360,13 +3361,16 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX) * r0 is used as a scratch register */ kvmppc_msr_interrupt: + andis. r0, r11, MSR_S@h rldicl r0, r11, 64 - MSR_TS_S_LG, 62 - cmpwi r0, 2 /* Check if we are in transactional state.. */ + cmpwi cr1, r0, 2 /* Check if we are in transactional state.. */ ld r11, VCPU_INTR_MSR(r9) - bne 1f + bne cr1, 1f /* ... if transactional, change to suspended */ li r0, 1 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG + beqlr + oris r11, r11, MSR_S@h /* preserve MSR_S bit setting */ blr /* -- 2.20.1
