On Tue, Nov 13, 2018 at 07:28:18PM +1100, Alexey Kardashevskiy wrote:
> At the moment NPU IOMMU is manipulated directly from the IODA2 PCI
> PE code; PCI PE acts as a master to NPU PE. Soon we will have compound
> IOMMU groups with several PEs from several different PHB (such as
> interconnected GPUs and NPUs) so there will be no single master but
> a one big IOMMU group.
>
> This makes a first step and converts an NPU PE to a table group.
>
> This should cause no behavioral change. Note that
> pnv_npu_release_ownership() has never been implemented.
>
> Signed-off-by: Alexey Kardashevskiy <aik@xxxxxxxxx>
Reviewed-by: David Gibson <david@xxxxxxxxxxxxxxxxxxxxx>
> ---
> arch/powerpc/platforms/powernv/pci.h | 5 ----
> arch/powerpc/platforms/powernv/npu-dma.c | 29 ++++++++++++++++++-----
> arch/powerpc/platforms/powernv/pci-ioda.c | 17 +++++++------
> 3 files changed, 33 insertions(+), 18 deletions(-)
>
> diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h
> index ddb4f02..cf9f748 100644
> --- a/arch/powerpc/platforms/powernv/pci.h
> +++ b/arch/powerpc/platforms/powernv/pci.h
> @@ -216,11 +216,6 @@ extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
> extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass);
> extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm);
> extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe);
> -extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
> - struct iommu_table *tbl);
> -extern long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num);
> -extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe);
> -extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe);
>
> /* pci-ioda-tce.c */
> #define POWERNV_IOMMU_DEFAULT_LEVELS 1
> diff --git a/arch/powerpc/platforms/powernv/npu-dma.c b/arch/powerpc/platforms/powernv/npu-dma.c
> index 4b60f43..1792c7e 100644
> --- a/arch/powerpc/platforms/powernv/npu-dma.c
> +++ b/arch/powerpc/platforms/powernv/npu-dma.c
> @@ -121,9 +121,11 @@ static struct pnv_ioda_pe *get_gpu_pci_dev_and_pe(struct pnv_ioda_pe *npe,
> return pe;
> }
>
> -long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
> +static long pnv_npu_set_window(struct iommu_table_group *table_group, int num,
> struct iommu_table *tbl)
> {
> + struct pnv_ioda_pe *npe = container_of(table_group, struct pnv_ioda_pe,
> + table_group);
> struct pnv_phb *phb = npe->phb;
> int64_t rc;
> const unsigned long size = tbl->it_indirect_levels ?
> @@ -155,8 +157,10 @@ long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
> return 0;
> }
>
> -long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num)
> +static long pnv_npu_unset_window(struct iommu_table_group *table_group, int num)
> {
> + struct pnv_ioda_pe *npe = container_of(table_group, struct pnv_ioda_pe,
> + table_group);
> struct pnv_phb *phb = npe->phb;
> int64_t rc;
>
> @@ -198,7 +202,8 @@ static void pnv_npu_dma_set_32(struct pnv_ioda_pe *npe)
> if (!gpe)
> return;
>
> - rc = pnv_npu_set_window(npe, 0, gpe->table_group.tables[0]);
> + rc = pnv_npu_set_window(&npe->table_group, 0,
> + gpe->table_group.tables[0]);
>
> /*
> * NVLink devices use the same TCE table configuration as
> @@ -223,7 +228,7 @@ static int pnv_npu_dma_set_bypass(struct pnv_ioda_pe *npe)
> if (phb->type != PNV_PHB_NPU_NVLINK || !npe->pdev)
> return -EINVAL;
>
> - rc = pnv_npu_unset_window(npe, 0);
> + rc = pnv_npu_unset_window(&npe->table_group, 0);
> if (rc != OPAL_SUCCESS)
> return rc;
>
> @@ -276,9 +281,12 @@ void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass)
> }
> }
>
> +#ifdef CONFIG_IOMMU_API
> /* Switch ownership from platform code to external user (e.g. VFIO) */
> -void pnv_npu_take_ownership(struct pnv_ioda_pe *npe)
> +static void pnv_npu_take_ownership(struct iommu_table_group *table_group)
> {
> + struct pnv_ioda_pe *npe = container_of(table_group, struct pnv_ioda_pe,
> + table_group);
> struct pnv_phb *phb = npe->phb;
> int64_t rc;
>
> @@ -289,7 +297,7 @@ void pnv_npu_take_ownership(struct pnv_ioda_pe *npe)
> * if it was enabled at the moment of ownership change.
> */
> if (npe->table_group.tables[0]) {
> - pnv_npu_unset_window(npe, 0);
> + pnv_npu_unset_window(&npe->table_group, 0);
> return;
> }
>
> @@ -304,6 +312,12 @@ void pnv_npu_take_ownership(struct pnv_ioda_pe *npe)
> pnv_pci_ioda2_tce_invalidate_entire(npe->phb, false);
> }
>
> +static struct iommu_table_group_ops pnv_pci_npu_ops = {
> + .set_window = pnv_npu_set_window,
> + .unset_window = pnv_npu_unset_window,
> + .take_ownership = pnv_npu_take_ownership,
> +};
> +
> struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe)
> {
> struct pnv_phb *phb = npe->phb;
> @@ -314,6 +328,8 @@ struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe)
> if (!gpe || !gpdev)
> return NULL;
>
> + npe->table_group.ops = &pnv_pci_npu_ops;
> +
> list_for_each_entry(npdev, &pbus->devices, bus_list) {
> gptmp = pnv_pci_get_gpu_dev(npdev);
>
> @@ -326,6 +342,7 @@ struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe)
>
> return gpe;
> }
> +#endif /* !CONFIG_IOMMU_API */
>
> /*
> * NPU2 ATS
> diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
> index 7caf373..04639ae 100644
> --- a/arch/powerpc/platforms/powernv/pci-ioda.c
> +++ b/arch/powerpc/platforms/powernv/pci-ioda.c
> @@ -2677,14 +2677,14 @@ static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group,
> return ret;
>
> if (table_group->tables[num2])
> - pnv_npu_unset_window(npe, num2);
> + npe->table_group.ops->unset_window(&npe->table_group, num2);
>
> - ret = pnv_npu_set_window(npe, num, tbl);
> + ret = npe->table_group.ops->set_window(&npe->table_group, num, tbl);
> if (ret) {
> pnv_pci_ioda2_unset_window(table_group, num);
> if (table_group->tables[num2])
> - pnv_npu_set_window(npe, num2,
> - table_group->tables[num2]);
> + npe->table_group.ops->set_window(&npe->table_group,
> + num2, table_group->tables[num2]);
> }
>
> return ret;
> @@ -2704,19 +2704,22 @@ static long pnv_pci_ioda2_npu_unset_window(
> if (!npe->table_group.tables[num])
> return 0;
>
> - ret = pnv_npu_unset_window(npe, num);
> + ret = npe->table_group.ops->unset_window(&npe->table_group, num);
> if (ret)
> return ret;
>
> if (table_group->tables[num2])
> - ret = pnv_npu_set_window(npe, num2, table_group->tables[num2]);
> + ret = npe->table_group.ops->set_window(&npe->table_group, num2,
> + table_group->tables[num2]);
>
> return ret;
> }
>
> static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group)
> {
> - pnv_npu_take_ownership(gpe_table_group_to_npe(table_group));
> + struct pnv_ioda_pe *npe = gpe_table_group_to_npe(table_group);
> +
> + npe->table_group.ops->take_ownership(&npe->table_group);
> pnv_ioda2_take_ownership(table_group);
> }
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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