On Thu, 17 Aug 2017 10:56:35 +0000 David Laight <David.Laight@xxxxxxxxxx> wrote: > From: Alex Williamson > > Sent: 16 August 2017 17:56 > ... > > Firmware pissing match... Processors running with 8k or less page size > > fall within the recommendations of the PCI spec for register alignment > > of MMIO regions of the device and this whole problem becomes less of an > > issue. > > Actually if qemu is causing the MSI-X table accesses to fault, why doesn't > it just lie to the guest about the physical address of the MSI-X table? > Then mmio access to anything in the same physical page will just work. That's an interesting idea, but now you need to add a BAR for the virtualized vector table, but you'll also need to support extending a BAR because there won't necessarily be a BAR available to add. Of course PCI requires natural alignment of BARs, thus an extra few bytes on the end doubles the BAR size. So also hope that if we need to extend a BAR that there's a relatively small one available. In either case you're changing the layout of the device from what the driver might expect. We try pretty hard with device assignment to leave things in the same place as they appear on bare metal, perhaps removing things, but not actually moving things. It might work in the majority of cases, but it seems a bit precarious overall. Thanks, Alex -- To unsubscribe from this list: send the line "unsubscribe kvm-ppc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
