Re: [RFC PATCH 06/10] KVM: PPC: Book3S HV: Implement architecture compatibility modes for POWER8

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Am 05.11.2013 um 04:53 schrieb Paul Mackerras <paulus@xxxxxxxxx>:

> On Mon, Nov 04, 2013 at 01:53:36PM +0100, Alexander Graf wrote:
>> 
>> On 06.09.2013, at 05:55, Paul Mackerras <paulus@xxxxxxxxx> wrote:
>> 
>>> This allows us to select architecture 2.05 (POWER6) or 2.06 (POWER7)
>>> compatibility modes on a POWER8 processor.
>>> 
>>> Signed-off-by: Paul Mackerras <paulus@xxxxxxxxx>
>>> ---
>>> arch/powerpc/include/asm/reg.h |  2 ++
>>> arch/powerpc/kvm/book3s_hv.c   | 16 +++++++++++++++-
>>> 2 files changed, 17 insertions(+), 1 deletion(-)
>>> 
>>> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
>>> index 4ca8b85..483e0a2 100644
>>> --- a/arch/powerpc/include/asm/reg.h
>>> +++ b/arch/powerpc/include/asm/reg.h
>>> @@ -315,6 +315,8 @@
>>> #define SPRN_PCR    0x152    /* Processor compatibility register */
>>> #define   PCR_VEC_DIS    (1ul << (63-0))    /* Vec. disable (pre POWER8) */
>>> #define   PCR_VSX_DIS    (1ul << (63-1))    /* VSX disable (pre POWER8) */
>>> +#define   PCR_TM_DIS    (1ul << (63-2))    /* Trans. memory disable (POWER8) */
>> 
>> Is this going to get used?
> 
> Perhaps not, but I thought it worthwhile to document that the bit
> exists.

But why not? Does that mean we allow TM to be used in p7 compat mode?

Alex

> 
> Paul.
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