I'm thinking of emulating the lwarx and stwcx instruction as follows 1) to emulate lwarx i will just do a load word instruction . In order to emulate lwarx correctly, i will need to setup a global reservation structure, which has a reservation entry for each CPU. Upon making the lwarx, i will set the internal reserve bit, then setup a snoop address. All writes to the memory block that the address is in will destroy the reservation in this structure. Since i'm not calling a direct lwarx instruction upon encountering a lwarx in guest this will not leave a reservation when i'm returning to guest. 2) Upon encountering a stwcx instruction in guest i can match the reservation address as stored in my global reservation structure. If it matches then i can fire a dummy lwarx first in host and then fire the stwcx. Will that work ? Thanks in advance On Tue, Mar 6, 2012 at 8:16 PM, Sethi Varun-B16395 <B16395@xxxxxxxxxxxxx> wrote: > Hi Aashish, > Following is an example of the linux code where it uses lwarx and stcwx. > > 1: lwarx %0,0,%3 # atomic_add\n\ > add %0,%2,%0\n" > PPC405_ERR77(0,%3) > " stwcx. %0,0,%3 \n\ > bne- 1b" > > As you would notice after stcwx it checks for equal bit in the cr register. So I think in your code > you should also update the cr register after stcwx for the guest. > > Regards > Varun >> -----Original Message----- >> From: kvm-ppc-owner@xxxxxxxxxxxxxxx [mailto:kvm-ppc- >> owner@xxxxxxxxxxxxxxx] On Behalf Of Aashish Mittal >> Sent: Tuesday, March 06, 2012 2:07 AM >> To: kvm-ppc@xxxxxxxxxxxxxxx >> Subject: Emulating lwarx and stwcx instructions in PowerPc BOOKE e500 >> >> Hi >> I'm working on powerpc booke architecture and my project requires me to >> remove read and write privileges on some pages. Due to this any >> instruction accessing these pages traps and i'm trying to emulate the >> behavior of these instructions. >> >> I've emulated lwarx and stwcx instruction but i think stwcx is not >> working correctly. The emulation i've written is written below >> >> case OP_31_XOP_LWARX: >> { >> ulong ret; >> ulong addr; >> int eh = inst & 0x00000001 ; >> kvm_gva_to_hva(vcpu,ea,&addr); >> /*lwarx RT RA RB EH*/ >> if(eh == 0) >> __asm__ __volatile__("lwarx %0,0,%1,0; isync":"=r" (ret) :"r" >> (addr)); >> else >> __asm__ __volatile__("lwarx %0,0,%1,1; isync":"=r" (ret) :"r" >> (addr)); >> >> kvmppc_set_gpr(vcpu,rt,ret); >> } >> >> case OP_31_XOP_STWCX: >> { >> ulong tmp; >> ulong addr; >> ulong data; >> kvm_gva_to_hva(vcpu,ea,&addr); >> kvmppc_read_guest(vcpu,ea,&data,sizeof(data)); >> __asm__ __volatile__("stwcx. %1,0,%2; isync" >> :"=r" (tmp):"r" (data),"r" (addr):"memory"); >> >> } >> >> Here kvm_gva_to_hva function convrets a guest effective address to host >> virtual address . >> >> void kvm_gva_to_hva(struct kvm_vcpu *vcpu, ulong ea,ulong* hva) { >> gfn_t gfn; >> gpa_t gpa ; >> int gtlb_index; >> int offset; >> ulong addr; >> struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu); >> >> gtlb_index = kvmppc_mmu_itlb_index(vcpu, ea); >> gpa = kvmppc_mmu_xlate(vcpu,gtlb_index, ea); >> gfn = gpa >> PAGE_SHIFT; >> addr = (ulong)gfn_to_hva(vcpu_e500->vcpu.kvm, gfn); >> offset = offset_in_page(gpa); >> >> *hva = addr + offset; >> return; >> } >> >> The guest just hangs once it encounters a stwcx instruction. Does anybody >> have any idea why this is not working and what's wrong about the >> emulation code. >> >> Also i'm working on linux-3.0-rc4 kernel . >> >> Thanks in advance >> >> >> -- >> To unsubscribe from this list: send the line "unsubscribe kvm-ppc" in the >> body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at >> http://vger.kernel.org/majordomo-info.html > > > -- > To unsubscribe from this list: send the line "unsubscribe kvm-ppc" in > the body of a message to majordomo@xxxxxxxxxxxxxxx > More majordomo info at http://vger.kernel.org/majordomo-info.html -- Thanks and regards Aashish Mittal Final year Dual Degree IIT delhi -- To unsubscribe from this list: send the line "unsubscribe kvm-ppc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
