On Tue, 14 Jun 2011 12:40:22 +0200
Alexander Graf <agraf@xxxxxxx> wrote:
>
> On 03.06.2011, at 01:17, Scott Wood wrote:
>
> > diff --git a/arch/powerpc/kvm/e500_tlb.c b/arch/powerpc/kvm/e500_tlb.c
> > index c09e642..9d1e28d 100644
> > --- a/arch/powerpc/kvm/e500_tlb.c
> > +++ b/arch/powerpc/kvm/e500_tlb.c
> > @@ -41,25 +41,14 @@ void kvmppc_dump_tlbs(struct kvm_vcpu *vcpu)
> >
> > for (tlbsel = 0; tlbsel < 2; tlbsel++) {
>
> The 2 here should be E500_TLB_NUM
This patch didn't change this line, and this whole function can come out
once we can dump the TLB with qemu.
> > +static inline void kvmppc_e500_setup_stlbe(struct kvmppc_vcpu_e500 *vcpu_e500,
> > + struct tlbe *gtlbe, int tsize,
> > + struct tlbe_priv *priv,
> > + u64 gvaddr, struct tlbe *stlbe)
> > +{
> > + pfn_t pfn = priv->pfn;
> > +
> > + /* Force TS=1 IPROT=0 for all guest mappings. */
> > + stlbe->mas1 = MAS1_TSIZE(tsize)
> > + | MAS1_TID(get_tlb_tid(gtlbe)) | MAS1_TS | MAS1_VALID;
> > + stlbe->mas2 = (gvaddr & MAS2_EPN)
> > + | e500_shadow_mas2_attrib(gtlbe->mas2,
> > + vcpu_e500->vcpu.arch.shared->msr & MSR_PR);
> > + stlbe->mas3 = ((pfn << PAGE_SHIFT) & MAS3_RPN)
> > + | e500_shadow_mas3_attrib(gtlbe->mas3,
> > + vcpu_e500->vcpu.arch.shared->msr & MSR_PR);
>
> This is another source of slowness. Guest PR should only be yet another bit to account for in the TID, so we can keep both active at the same time. That should be possible with the shadow PID code, right?
Not sure what you mean. We do account for guest PR with a separate shadow
PID. The forcing of MSR_PR here is still needed because we still always
run the guest with the real MSR[PR] set.
-Scott
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