On Tue, 2008-06-03 at 13:50 -0500, Jerone Young wrote: > This patch fixes definitions for bit in the dbcr register for 44x > processor. Some definitions are shared,but according to the PowerPC 440 > Users Manual (p 201). > > Will send other patches for dbcr1 & dbcr2 as these are where PPC440 > sets it's comparison modes for debug registers. > > Signed-off-by: Jerone Young <jyoung5@xxxxxxxxxx> > > diff --git a/include/asm-powerpc/reg_booke.h b/include/asm-powerpc/reg_booke.h > --- a/include/asm-powerpc/reg_booke.h > +++ b/include/asm-powerpc/reg_booke.h > @@ -253,6 +253,29 @@ > #define ESR_BO 0x00020000 /* Byte Ordering */ > > /* Bit definitions related to the DBCR0. */ > +#if defined(CONFIG_44x) > +#define DBCR0_EDM 0x80000000 /* External Debug Mode */ > +#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ > +#define DBCR0_RST 0x30000000 /* all the bits in the RST field */ > +#define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */ > +#define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */ > +#define DBCR0_RST_CORE 0x10000000 /* Core Reset */ > +#define DBCR0_RST_NONE 0x00000000 /* No Reset */ > +#define DBCR0_IC 0x08000000 /* Instruction Completion */ > +#define DBCR0_BT 0x04000000 /* Branch Taken */ > +#define DBCR0_EDE 0x02000000 /* Exception Debug Event */ > +#define DBCR0_TDE 0x01000000 /* TRAP Debug Event */ > +#define DBCR0_IA1 0x00800000 /* Instr Addr compare 1 enable */ > +#define DBCR0_IA2 0x00400000 /* Instr Addr compare 2 enable */ > +#define DBCR0_IA3 0x00200000 /* Instr Addr compare 3 enable */ > +#define DBCR0_IA4 0x00100000 /* Instr Addr compare 4 enable */ > +#define DBCR0_DAC1R 0x00080000 /* DAC 1 Read enable */ > +#define DBCR0_DAC1W 0x00040000 /* DAC 1 Write enable */ > +#define DBCR0_DAC2R 0x00020000 /* DAC 2 Read enable */ > +#define DBCR0_DAC2W 0x00010000 /* DAC 2 Write enable */ > +#define DBCR0_RET 0x00008000 /* Return Debug Event */ > +#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ > +#else > #define DBCR0_EDM 0x80000000 /* External Debug Mode */ > #define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ > #define DBCR0_RST 0x30000000 /* all the bits in the RST field */ > @@ -275,6 +298,7 @@ > #define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */ > #define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */ > #define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ > +#endif Make sure you use the right ifdefs. It looks to me like the bit positions on e500, 440, and Book E all match, while 405 is the odd one out, and currently only the 405 positions are defined. Please confirm and update your patch accordingly. Also, you should send all the definitions in the same patch; I don't see any reason to split them up. -- Hollis Blanchard IBM Linux Technology Center -- To unsubscribe from this list: send the line "unsubscribe kvm-ppc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html