Xu, Anthony wrote:
Hi all,
Thanks for your comments.
I made this new patch based on your comments
1. use bimodal _PRT, to take advantage of IOAPIC pin 16~23
the mapping is simple, slot -> (slot&7)+16 IOAPIC pin,
someone may provide good mapping ?
I think it's fine. If we find a better one later, or if we add another
ioapic, we can easily change it since the bios and qemu are shipped as a
unit.
2. use ISA-bridge configure space 0x64 byte as a communication
mechansim.
When guest BIOS invokes _PIC, the value is passed to qemu
through byte 0x64.
qemu know whether it is PIC mode and APIC mode by checking
byte 0x64.
3. pci_slot_get_pirq and piix3_set_irq adopt different operation based
on PIC mode/APIC mode
I'm not sure how real hardware works, but I _think_ that it routes irqs
unconditionally to both the legacy path and directly to the ioapic. So
for example if slot 5 asserts an interrupt, we map it through the pci
link mapping and generate an active high interrupt to one of {5, 10, 11}
(both pic and ioapic), and simultaneously an active low interrupt to
ioapic pin 21.
The _PIC method should disable the link interrupts if ioapic mode is
disabled.
This removes the need for communication between the bios and qemu.
+ /* APIC and PIC flag */
+ OperationRegion (P40D, PCI_Config, 0x64, 0x01)
+
This is actually SERIRQC, serial irq control.
+
+#ifdef KVM_CAP_IRQCHIP
This should be unconditional.
+static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
+{
+ int slot_addend;
+ if( piix3_dev->config[0x64]) // APIC mode
+ return ((pci_dev->devfn >> 3) & 7)+16;
+ else { // PIC mode
+ slot_addend = (pci_dev->devfn >> 3) - 1;
+ return (irq_num + slot_addend) & 3;
+ }
+}
What I'm suggesting is to "fork" the interrupt into two lines, one
legacy path and the ioapic path.
--
I have a truly marvellous patch that fixes the bug which this
signature is too narrow to contain.
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