Marcelo Tosatti wrote: > On Tue, Jun 10, 2008 at 03:57:30PM +0800, Xu, Anthony wrote: >> diff --git a/qemu/hw/pci.c b/qemu/hw/pci.c >> index a23a466..df0ea33 100644 >> --- a/qemu/hw/pci.c >> +++ b/qemu/hw/pci.c >> @@ -548,7 +548,7 @@ static void pci_set_irq(void *opaque, int >> irq_num, int level) pci_dev = bus->parent_dev; >> } >> bus->irq_count[irq_num] += change; >> - bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] >> != 0); + bus->set_irq(bus->irq_opaque, irq_num, >> !(bus->irq_count[irq_num] != 0)); } > > Ideally this should detect if the PCI interrupts are active low or > high and act accordingly (so that older BIOSes still work and no > assumptions are made). Will probably have to be done anyway for > merging into QEMU. As I mentioned before, all PCI devices in Qemu used active high level-triggerred interrupt. While IOAPIC pin with fixed connection to slot uses active low level-triggerred interrupt by default. Seems we need to find a place to reverse it. > > One way of doing it would be to talk to ACPI via a new SystemIO > region, but there must be an easier way. Good point, qemu needs to know whether it is in PIC mode or in APIC mode. We need define the communication mechanism, SystemIO region is one choice. Thanks, Anthony -- To unsubscribe from this list: send the line "unsubscribe kvm-ia64" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
