As a minor optimisation, we can retrofit the "S1PTW is a write
even on translation fault" concept *if* the vcpu is using the
HW-managed Access Flag, as setting TCR_EL1.HA is guaranteed
to result in an update of the PTE.
However, we cannot do the same thing for DB, as it would require
us to parse the PTs to find out if the DBM bit is set there.
This is not going to happen.
Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
---
arch/arm64/include/asm/kvm_emulate.h | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h
index fd6ad8b21f85..4ee467065042 100644
--- a/arch/arm64/include/asm/kvm_emulate.h
+++ b/arch/arm64/include/asm/kvm_emulate.h
@@ -374,6 +374,9 @@ static __always_inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu)
static inline bool kvm_is_write_fault(struct kvm_vcpu *vcpu)
{
if (kvm_vcpu_abt_iss1tw(vcpu)) {
+ unsigned int afdb;
+ u64 mmfr1;
+
/*
* Only a permission fault on a S1PTW should be
* considered as a write. Otherwise, page tables baked
@@ -385,12 +388,27 @@ static inline bool kvm_is_write_fault(struct kvm_vcpu *vcpu)
* to map the page containing the PT (read only at
* first), then a permission fault to allow the flags
* to be set.
+ *
+ * We can improve things if the guest uses AF, as this
+ * is guaranteed to result in a write to the PTE. For
+ * DB, however, we'd need to parse the guest's PTs,
+ * and that's not on. DB is crap anyway.
*/
switch (kvm_vcpu_trap_get_fault_type(vcpu)) {
case ESR_ELx_FSC_PERM:
return true;
default:
- return false;
+ /* Can't introspect TCR_EL1 with pKVM */
+ if (kvm_vm_is_protected(vcpu->kvm))
+ return false;
+
+ mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
+ afdb = cpuid_feature_extract_unsigned_field(mmfr1, ID_AA64MMFR1_EL1_HAFDBS_SHIFT);
+
+ if (afdb == ID_AA64MMFR1_EL1_HAFDBS_NI)
+ return false;
+
+ return (vcpu_read_sys_reg(vcpu, TCR_EL1) & TCR_HA);
}
}
--
2.34.1
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