Before this change, the cache configuration of the physical CPU was exposed to vcpus. This is problematic because the cache configuration a vcpu sees varies when it migrates between vcpus with different cache configurations. Fabricate cache configuration from the sanitized value, which holds the CTR_EL0 value the userspace sees regardless of which physical CPU it resides on. V2 -> V3: - Corrected message for patch "Normalize cache configuration" - Split patch "Normalize cache configuration" - Added handling for CSSELR_EL1.TnD - Added code to ignore RES0 in CSSELR_EL1 - Replaced arm64_ftr_reg_ctrel0.sys_val with read_sanitised_ftr_reg(SYS_CTR_EL0) - Fixed vcpu->arch.ccsidr initialziation - Added CCSIDR_EL1 sanitization - Added FWB check - Added a comment for CACHE_TYPE_SEPARATE - Added MTE tag cache creation code for CLIDR_EL1 fabrication - Removed CLIDR_EL1 reset code for reset caused by guest - Added a comment for CCSIDR2 V2: https://lore.kernel.org/lkml/20221211051700.275761-2-akihiko.odaki@xxxxxxxxxx/ V1: https://lore.kernel.org/lkml/525ff263-90b3-5b12-da31-171b09f9ad1b@xxxxxxxxxx/ Akihiko Odaki (7): arm64/sysreg: Convert CCSIDR_EL1 to automatic generation arm64/sysreg: Add CCSIDR2_EL1 arm64/cache: Move CLIDR macro definitions KVM: arm64: Always set HCR_TID2 KVM: arm64: Allow user to set CCSIDR_EL1 KVM: arm64: Mask FEAT_CCIDX KVM: arm64: Normalize cache configuration arch/arm64/include/asm/cache.h | 9 + arch/arm64/include/asm/kvm_arm.h | 3 +- arch/arm64/include/asm/kvm_emulate.h | 4 - arch/arm64/include/asm/kvm_host.h | 6 +- arch/arm64/include/asm/sysreg.h | 1 - arch/arm64/kernel/cacheinfo.c | 5 - arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 2 - arch/arm64/kvm/reset.c | 1 + arch/arm64/kvm/sys_regs.c | 246 +++++++++++++-------- arch/arm64/tools/sysreg | 16 ++ 10 files changed, 182 insertions(+), 111 deletions(-) -- 2.38.1 _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
