Before this change, the cache configuration of the physical CPU was exposed to vcpus. This is problematic because the cache configuration a vcpu sees varies when it migrates between vcpus with different cache configurations. Fabricate cache configuration from arm64_ftr_reg_ctrel0.sys_val, which holds the CTR_EL0 value the userspace sees regardless of which physical CPU it resides on. HCR_TID2 is now always set as it is troublesome to detect the difference of cache configurations among physical CPUs. CSSELR_EL1 is now held in the memory instead of the corresponding phyisccal register as the fabricated cache configuration may have a cache level which does not exist in the physical CPU, and setting the physical CSSELR_EL1 for the level results in an UNKNOWN behavior. CLIDR_EL1 and CCSIDR_EL1 are now writable from the userspace so that the VMM can restore the values saved with the old kernel. Akihiko Odaki (3): arm64/sysreg: Add CCSIDR2_EL1 arm64/cache: Move CLIDR macro definitions KVM: arm64: Normalize cache configuration arch/arm64/include/asm/cache.h | 6 + arch/arm64/include/asm/kvm_arm.h | 3 +- arch/arm64/include/asm/kvm_emulate.h | 4 - arch/arm64/include/asm/kvm_host.h | 6 +- arch/arm64/kernel/cacheinfo.c | 5 - arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 2 - arch/arm64/kvm/reset.c | 1 + arch/arm64/kvm/sys_regs.c | 232 ++++++++++++--------- arch/arm64/tools/sysreg | 5 + 9 files changed, 153 insertions(+), 111 deletions(-) -- 2.38.1 _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
