On Wed, Oct 19, 2022 at 02:11:26PM -0500, Rob Herring wrote: > Convert all the SPE register defines to automatic generation. No > functional changes. > > New registers and fields for SPEv1.2 are added with the conversion. > > Some of the PMBSR MSS field defines are kept as the automatic generation > has no way to create multiple names for the same register bits. The > meaning of the MSS field depends on other bits. A few small things below from checking against DDI0487I.a, nothing major: > +Sysreg PMSCR_EL1 3 0 9 9 0 > +Res0 63:8 > +Field 7:6 PCT Given the potential multiple meanings depending on both integration and runtime configuration representing this as a field seems sensible. > +Sysreg PMSNEVFR_EL1 3 0 9 9 1 > +Field 63:0 E > +EndSysreg While this does look rather different to the spec it does appear to be a sensible interpretation - the intent is clearly to have a mask of feature bits. > +Sysreg PMSIDR_EL1 3 0 9 9 7 > +Field 23:20 FORMAT > +Field 19:16 COUNTSIZE > +Field 15:12 MAXSIZE > +Field 11:8 INTERVAL These should really be enums. > +Sysreg PMBLIMITR_EL1 3 0 9 10 0 > +Enum 2:1 FM > + 0b0000 STOP_IRQ > +EndEnum DDI0487I.a also defines 0b01 DISCARD from FEAT_SPEv1p2. Also this is a two bit field so 0b00 would be a bit better. > +Sysreg PMBSR_EL1 3 0 9 10 3 > +Res0 63:32 > +Enum 31:26 EC > + 0b000000 BUF > + 0b100100 FAULT_S1 > + 0b100101 FAULT_S2 > +EndEnum DDI0487I.a also has 0b011110 FAULT_GPC 0b011111 IMP_DEF (the former from FEAT_RME). > +Sysreg PMBIDR_EL1 3 0 9 10 7 > +Res0 63:12 > +Field 11:8 EA This looks like it should be described as an enum. > +Field 3:0 ALIGN This could potentially also be an enum. > +Sysreg PMSCR_EL2 3 4 9 9 0 > +Res0 63:8 > +Field 7:6 PCT This lookslike it should be an enum.
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