On Tue, Apr 12, 2022 at 02:12:54PM +0100, Marc Zyngier wrote: > Starting with FEAT_WFXT in ARMv8.7, the TI field in the ISS > that is reported on a WFx trap is expanded by one bit to > allow the description of WFET and WFIT. > > Special care is taken to exclude the WFxT bit from the mask > used to match WFI so that it also matches WFIT when trapped from > EL0. > > Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx> > --- > arch/arm64/include/asm/esr.h | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h > index d52a0b269ee8..65c2201b11b2 100644 > --- a/arch/arm64/include/asm/esr.h > +++ b/arch/arm64/include/asm/esr.h > @@ -133,7 +133,8 @@ > #define ESR_ELx_CV (UL(1) << 24) > #define ESR_ELx_COND_SHIFT (20) > #define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT) > -#define ESR_ELx_WFx_ISS_TI (UL(1) << 0) > +#define ESR_ELx_WFx_ISS_TI (UL(3) << 0) > +#define ESR_ELx_WFx_ISS_WFxT (UL(2) << 0) > #define ESR_ELx_WFx_ISS_WFI (UL(0) << 0) > #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0) > #define ESR_ELx_xVC_IMM_MASK ((1UL << 16) - 1) > @@ -146,7 +147,8 @@ > #define DISR_EL1_ESR_MASK (ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC) > > /* ESR value templates for specific events */ > -#define ESR_ELx_WFx_MASK (ESR_ELx_EC_MASK | ESR_ELx_WFx_ISS_TI) > +#define ESR_ELx_WFx_MASK (ESR_ELx_EC_MASK | \ > + (ESR_ELx_WFx_ISS_TI & ~ESR_ELx_WFx_ISS_WFxT)) > #define ESR_ELx_WFx_WFI_VAL ((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) | \ > ESR_ELx_WFx_ISS_WFI) > Reviewed-by: Joey Gouly <joey.gouly@xxxxxxx> _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
