Re: [PATCH v6 11/25] KVM: arm64: Add remaining ID registers to id_reg_desc_table

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



On Wed, Mar 23, 2022 at 08:44:26PM +0000, Oliver Upton wrote:
> On Wed, Mar 23, 2022 at 01:13:32PM -0700, Ricardo Koller wrote:
> > On Wed, Mar 23, 2022 at 07:53:14PM +0000, Oliver Upton wrote:
> > > Hi Reiji,
> > > 
> > > On Thu, Mar 10, 2022 at 08:47:57PM -0800, Reiji Watanabe wrote:
> > > > Add hidden or reserved ID registers, and remaining ID registers,
> > > > which don't require special handling, to id_reg_desc_table.
> > > > Add 'flags' field to id_reg_desc, which is used to indicates hiddden
> > > > or reserved registers. Since now id_reg_desc_init() is called even
> > > > for hidden/reserved registers, change it to not do anything for them.
> > > > 
> > > > Signed-off-by: Reiji Watanabe <reijiw@xxxxxxxxxx>
> > > 
> > > I think there is a very important detail of the series that probably
> > > should be highlighted. We are only allowing AArch64 feature registers to
> > > be configurable, right? AArch32 feature registers remain visible with
> > > their default values passed through to the guest. If you've already
> > > stated this as a precondition elsewhere then my apologies for the noise.
> > 
> > Aren't AArch64 ID regs architecturally mapped to their AArch32
> > counterparts?  They should show the same values.  I'm not sure if it's a
> > problem (and if KVM is faithful to that rule),
> 
> I believe it's a bit more subtle than that. The AArch32 feature registers
> are architecturally mapped to certain encodings accessible from AArch64.
> For example, ID_PFR0_EL1 is actually a 64 bit register where bits [31:0]
> map to the ID_PFR0 AArch32 register. ID_PFR0_EL1 is only accessible from
> AArch64 with the MRS instruction, and ID_PFR0 is only accessible from
> AArch32 with the MRC instruction. KVM just so happens to handle both of
> these reads from the same sys_reg_desc.
> 
> AFAIK, there does not exist a direct bit mapping between the
> ID_*_EL1 <-> ID_AA64*_EL1 registers. But hey, could be wrong :)

I think you are right. ID_PFR0_EL1[31:0] doesn't even have the same
field as ID_AA64PFR0_EL1[31:0]. The only exception would be RAS which is
at [31:28] on both, but it doesn't say anywhere that ID_PFR0_EL1.RAS
maps architecturally to ID_AA64PFR0_EL1.RAS. So, I think we can assume
it doesn't (?).

Thanks,
Ricardo

> 
> --
> Thanks,
> Oliver
_______________________________________________
kvmarm mailing list
kvmarm@xxxxxxxxxxxxxxxxxxxxx
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm



[Index of Archives]     [Linux KVM]     [Spice Development]     [Libvirt]     [Libvirt Users]     [Linux USB Devel]     [Linux Audio Users]     [Yosemite News]     [Linux Kernel]     [Linux SCSI]

  Powered by Linux