Hi Marc,
> On 28 Jan 2022, at 11:18, Marc Zyngier <maz@xxxxxxxxxx> wrote:
>
> From: Christoffer Dall <christoffer.dall@xxxxxxx>
>
> When running a nested hypervisor we commonly have to figure out if
> the VCPU mode is running in the context of a guest hypervisor or guest
> guest, or just a normal guest.
>
> Add convenient primitives for this.
>
> Reviewed-by: Russell King (Oracle) <rmk+kernel@xxxxxxxxxxxxxxx>
> Signed-off-by: Christoffer Dall <christoffer.dall@xxxxxxx>
> Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
> ---
> arch/arm64/include/asm/kvm_emulate.h | 53 ++++++++++++++++++++++++++++
> 1 file changed, 53 insertions(+)
>
> diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h
> index d62405ce3e6d..ea9a130c4b6a 100644
> --- a/arch/arm64/include/asm/kvm_emulate.h
> +++ b/arch/arm64/include/asm/kvm_emulate.h
> @@ -178,6 +178,59 @@ static __always_inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num,
> vcpu_gp_regs(vcpu)->regs[reg_num] = val;
> }
>
> +static inline bool vcpu_is_el2_ctxt(const struct kvm_cpu_context *ctxt)
> +{
> + switch (ctxt->regs.pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) {
> + case PSR_MODE_EL2h:
> + case PSR_MODE_EL2t:
> + return true;
> + default:
> + return false;
> + }
> +}
PSR_MODE_EL2{h,t} values the least significant nibble, so why the PSR_MODE32_BIT in the condition?
For the scope of this function as is, may I suggest:
switch (ctxt->regs.pstate & PSR_MODE_MASK) {
which should be sufficient to check if vcpu_is_el2_ctx.
Thank you.
Miguel
> +
> +static inline bool vcpu_is_el2(const struct kvm_vcpu *vcpu)
> +{
> + return vcpu_is_el2_ctxt(&vcpu->arch.ctxt);
> +}
> +
> +static inline bool __vcpu_el2_e2h_is_set(const struct kvm_cpu_context *ctxt)
> +{
> + return ctxt_sys_reg(ctxt, HCR_EL2) & HCR_E2H;
> +}
> +
> +static inline bool vcpu_el2_e2h_is_set(const struct kvm_vcpu *vcpu)
> +{
> + return __vcpu_el2_e2h_is_set(&vcpu->arch.ctxt);
> +}
> +
> +static inline bool __vcpu_el2_tge_is_set(const struct kvm_cpu_context *ctxt)
> +{
> + return ctxt_sys_reg(ctxt, HCR_EL2) & HCR_TGE;
> +}
> +
> +static inline bool vcpu_el2_tge_is_set(const struct kvm_vcpu *vcpu)
> +{
> + return __vcpu_el2_tge_is_set(&vcpu->arch.ctxt);
> +}
> +
> +static inline bool __is_hyp_ctxt(const struct kvm_cpu_context *ctxt)
> +{
> + /*
> + * We are in a hypervisor context if the vcpu mode is EL2 or
> + * E2H and TGE bits are set. The latter means we are in the user space
> + * of the VHE kernel. ARMv8.1 ARM describes this as 'InHost'
> + */
> + return vcpu_is_el2_ctxt(ctxt) ||
> + (__vcpu_el2_e2h_is_set(ctxt) && __vcpu_el2_tge_is_set(ctxt)) ||
> + WARN_ON(__vcpu_el2_tge_is_set(ctxt));
> +}
> +
> +static inline bool is_hyp_ctxt(const struct kvm_vcpu *vcpu)
> +{
> + return __is_hyp_ctxt(&vcpu->arch.ctxt);
> +}
> +
> /*
> * The layout of SPSR for an AArch32 state is different when observed from an
> * AArch64 SPSR_ELx or an AArch32 SPSR_*. This function generates the AArch32
> --
> 2.30.2
>
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