On Tue, 18 Jan 2022 16:36:59 +0000, Alexandru Elisei <alexandru.elisei@xxxxxxx> wrote: > > Hi Marc, > > On Mon, Nov 29, 2021 at 08:00:57PM +0000, Marc Zyngier wrote: > > From: Christoffer Dall <christoffer.dall@xxxxxxx> > > > > When a guest hypervisor running virtual EL2 in EL1 executes an ERET > > instruction, we will have set HCR_EL2.NV which traps ERET to EL2, so > > that we can emulate the exception return in software. > > > > Signed-off-by: Christoffer Dall <christoffer.dall@xxxxxxx> > > Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx> > > --- > > arch/arm64/include/asm/esr.h | 5 +++++ > > arch/arm64/include/asm/kvm_arm.h | 2 +- > > arch/arm64/kvm/handle_exit.c | 10 ++++++++++ > > 3 files changed, 16 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h > > index d52a0b269ee8..6835e4231119 100644 > > --- a/arch/arm64/include/asm/esr.h > > +++ b/arch/arm64/include/asm/esr.h > > @@ -257,6 +257,11 @@ > > (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \ > > ESR_ELx_SYS64_ISS_OP2_SHIFT)) > > > > +/* ISS field definitions for ERET/ERETAA/ERETAB trapping */ > > + > > +#define ESR_ELx_ERET_ISS_ERET_ERETAx 0x2 > > +#define ESR_ELx_ERET_ISS_ERETA_ERATAB 0x1 > ^^^^^ > Shouldn't that be ERETAA? Hmm, this is rather ambiguous indeed. I'm going to repaint it as: #define ESR_ELx_ERET_ISS_ERET 0x2 #define ESR_ELx_ERET_ISS_ERETA 0x1 which matches the ARM ARM wording as of DDI0487G.b. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
