On Wed, 17 Nov 2021 06:43:34 +0000,
Reiji Watanabe <reijiw@xxxxxxxxxx> wrote:
>
> This patch adds id_reg_info for ID_AA64PFR0_EL1 to make it writable by
> userspace.
>
> The CSV2/CSV3 fields of the register were already writable and values
> that were written for them affected all vCPUs before. Now they only
> affect the vCPU.
> Return an error if userspace tries to set SVE/GIC field of the register
> to a value that conflicts with SVE/GIC configuration for the guest.
> SIMD/FP/SVE fields of the requested value are validated according to
> Arm ARM.
>
> Signed-off-by: Reiji Watanabe <reijiw@xxxxxxxxxx>
> ---
> arch/arm64/kvm/sys_regs.c | 159 ++++++++++++++++++++++++--------------
> 1 file changed, 103 insertions(+), 56 deletions(-)
>
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index 1552cd5581b7..35400869067a 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -401,6 +401,92 @@ static void id_reg_info_init(struct id_reg_info *id_reg)
> id_reg->init(id_reg);
> }
>
> +#define kvm_has_gic3(kvm) \
> + (irqchip_in_kernel(kvm) && \
> + (kvm)->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
> +
> +static int validate_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
> + const struct id_reg_info *id_reg, u64 val)
> +{
> + int fp, simd;
> + bool vcpu_has_sve = vcpu_has_sve(vcpu);
> + bool pfr0_has_sve = id_aa64pfr0_sve(val);
> + int gic;
> +
> + simd = cpuid_feature_extract_signed_field(val, ID_AA64PFR0_ASIMD_SHIFT);
> + fp = cpuid_feature_extract_signed_field(val, ID_AA64PFR0_FP_SHIFT);
> + if (simd != fp)
> + return -EINVAL;
> +
> + /* fp must be supported when sve is supported */
> + if (pfr0_has_sve && (fp < 0))
> + return -EINVAL;
> +
> + /* Check if there is a conflict with a request via KVM_ARM_VCPU_INIT */
> + if (vcpu_has_sve ^ pfr0_has_sve)
> + return -EPERM;
> +
> + gic = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_GIC_SHIFT);
> + if ((gic > 0) ^ kvm_has_gic3(vcpu->kvm))
> + return -EPERM;
> +
> + return 0;
> +}
> +
> +static void init_id_aa64pfr0_el1_info(struct id_reg_info *id_reg)
> +{
> + u64 limit = id_reg->vcpu_limit_val;
> + unsigned int gic;
> +
> + limit &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_AMU);
> + if (!system_supports_sve())
> + limit &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_SVE);
> +
> + /*
> + * The default is to expose CSV2 == 1 and CSV3 == 1 if the HW
> + * isn't affected. Userspace can override this as long as it
> + * doesn't promise the impossible.
> + */
> + limit &= ~(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV2) |
> + ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3));
> +
> + if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED)
> + limit |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV2), 1);
> + if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED)
> + limit |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3), 1);
> +
> + gic = cpuid_feature_extract_unsigned_field(limit, ID_AA64PFR0_GIC_SHIFT);
> + if (gic > 1) {
> + /* Limit to GICv3.0/4.0 */
> + limit &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_GIC);
> + limit |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_GIC), 1);
> + }
> + id_reg->vcpu_limit_val = limit;
> +}
> +
> +static u64 get_reset_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
> + const struct id_reg_info *idr)
> +{
> + u64 val = idr->vcpu_limit_val;
> +
> + if (!vcpu_has_sve(vcpu))
> + val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_SVE);
> +
> + if (!kvm_has_gic3(vcpu->kvm))
> + val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_GIC);
No. As I said in a previous email, this breaks migration, and
advertising a GICv3 CPU interface doesn't mean it is usable (the guest
OS must check that it can actually enable ICC_SRE_EL1.SRE -- see what
the Linux GICv3 driver does for an example).
> +
> + return val;
> +}
> +
> +static struct id_reg_info id_aa64pfr0_el1_info = {
> + .sys_reg = SYS_ID_AA64PFR0_EL1,
> + .ftr_check_types = S_FCT(ID_AA64PFR0_ASIMD_SHIFT, FCT_LOWER_SAFE) |
> + S_FCT(ID_AA64PFR0_FP_SHIFT, FCT_LOWER_SAFE),
> + .init = init_id_aa64pfr0_el1_info,
> + .validate = validate_id_aa64pfr0_el1,
> + .get_reset_val = get_reset_id_aa64pfr0_el1,
> +};
> +
> /*
> * An ID register that needs special handling to control the value for the
> * guest must have its own id_reg_info in id_reg_info_table.
> @@ -409,7 +495,9 @@ static void id_reg_info_init(struct id_reg_info *id_reg)
> * validation, etc.)
> */
> #define GET_ID_REG_INFO(id) (id_reg_info_table[IDREG_IDX(id)])
> -static struct id_reg_info *id_reg_info_table[KVM_ARM_ID_REG_MAX_NUM] = {};
> +static struct id_reg_info *id_reg_info_table[KVM_ARM_ID_REG_MAX_NUM] = {
> + [IDREG_IDX(SYS_ID_AA64PFR0_EL1)] = &id_aa64pfr0_el1_info,
> +};
>
> static int validate_id_reg(struct kvm_vcpu *vcpu,
> const struct sys_reg_desc *rd, u64 val)
> @@ -1239,20 +1327,22 @@ static bool access_arch_timer(struct kvm_vcpu *vcpu,
> static u64 __read_id_reg(const struct kvm_vcpu *vcpu, u32 id)
> {
> u64 val = __vcpu_sys_reg(vcpu, IDREG_SYS_IDX(id));
> + u64 lim, gic, gic_lim;
> + const struct id_reg_info *id_reg;
>
> switch (id) {
> case SYS_ID_AA64PFR0_EL1:
> - if (!vcpu_has_sve(vcpu))
> - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_SVE);
> - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_AMU);
> - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_CSV2);
> - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2);
> - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3);
> - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3);
> - if (irqchip_in_kernel(vcpu->kvm) &&
> - vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
> - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_GIC);
> - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_GIC), 1);
> + gic = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_GIC_SHIFT);
> + if (kvm_has_gic3(vcpu->kvm) && (gic == 0)) {
> + /*
> + * This is a case where userspace configured gic3 after
> + * the vcpu was created, and then it didn't set
> + * ID_AA64PFR0_EL1.
> + */
Shouldn't that be done at the point where a GICv3 is created, rather
than after the fact?
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
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