On Fri, Aug 06, 2021 at 01:42:42PM +0100, Will Deacon wrote:
> On Fri, Aug 06, 2021 at 12:59:28PM +0100, Catalin Marinas wrote:
> > On Fri, Aug 06, 2021 at 12:31:04PM +0100, Will Deacon wrote:
> > > diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h
> > > index 75beffe2ee8a..e9c30859f80c 100644
> > > --- a/arch/arm64/include/asm/mmu.h
> > > +++ b/arch/arm64/include/asm/mmu.h
> > > @@ -27,11 +27,32 @@ typedef struct {
> > > } mm_context_t;
> > >
> > > /*
> > > - * This macro is only used by the TLBI and low-level switch_mm() code,
> > > - * neither of which can race with an ASID change. We therefore don't
> > > - * need to reload the counter using atomic64_read().
> > > + * We use atomic64_read() here because the ASID for an 'mm_struct' can
> > > + * be reallocated when scheduling one of its threads following a
> > > + * rollover event (see new_context() and flush_context()). In this case,
> > > + * a concurrent TLBI (e.g. via try_to_unmap_one() and ptep_clear_flush())
> > > + * may use a stale ASID. This is fine in principle as the new ASID is
> > > + * guaranteed to be clean in the TLB, but the TLBI routines have to take
> > > + * care to handle the following race:
> > > + *
> > > + * CPU 0 CPU 1 CPU 2
> > > + *
> > > + * // ptep_clear_flush(mm)
> > > + * xchg_relaxed(pte, 0)
> > > + * DSB ISHST
> > > + * old = ASID(mm)
> >
> > We'd need specs clarified (ARM ARM, cat model) that the DSB ISHST is
> > sufficient to order the pte write with the subsequent ASID read.
>
> Although I agree that the cat model needs updating and also that the Arm
> ARM isn't helpful by trying to define DMB and DSB at the same time, it
> does clearly state the following:
>
> // B2-149
> | A DSB instruction executed by a PE, PEe, completes when all of the
> | following apply:
> |
> | * All explicit memory accesses of the required access types appearing
> | in program order before the DSB are complete for the set of observers
> | in the required shareability domain.
>
> [...]
>
> // B2-150
> | In addition, no instruction that appears in program order after the
> | DSB instruction can alter any state of the system or perform any part
> | of its functionality until the DSB completes other than:
> |
> | * Being fetched from memory and decoded.
> | * Reading the general-purpose, SIMD and floating-point, Special-purpose,
> | or System registers that are directly or indirectly read without
> | causing side-effects.
>
> Which means that the ASID read cannot return its data before the DSB ISHST
> has completed and the DSB ISHST cannot complete until the PTE write has
> completed.
Thanks for the explanation.
> > Otherwise the patch looks fine to me:
> >
> > Reviewed-by: Catalin Marinas <catalin.marinas@xxxxxxx>
>
> Thanks! Do you want to queue it for 5.15? I don't think there's a need to
> rush it into 5.14 given that we don't have any evidence of it happening
> in practice.
Happy to queue it for 5.15.
--
Catalin
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