Hi Will, On 7/22/21 4:38 PM, Will Deacon wrote: > Hi Vladimir, > > On Thu, Jul 22, 2021 at 04:22:26PM +0100, Vladimir Murzin wrote: >> On 7/22/21 10:50 AM, Will Deacon wrote: >>> As an aside: I'm more and more inclined to rip out the CnP stuff given >>> that it doesn't appear to being any benefits, but does have some clear >>> downsides. Perhaps something for next week. >> >> Can you please clarify what do you mean by "it doesn't appear to being any >> benefits"? IIRC, Cortex-A65 implements CnP hint and I've heard that some >> payloads seen improvement... > > Has anybody taped that out? I'd have thought building an SMT design in 2021 > is a reasonably courageous thing to do. As you said three can be niche for that... > > The issue I'm getting at is that modern cores seem to advertise CnP even > if they ignore it internally, maybe because of some big/little worries? Should we employ CPU errata framework for such cores to demote CnP? > That would be fine if it didn't introduce complexity and overhead to the > kernel, but it does and therefore I think we should rip it out (or at > least stick it behind a "default n" config option if there are some niche > users). "default n" still better then no code at all :) Cheers Vladimir > > There are also open questions as to exactly what CnP does because the > architecture is not clear at all (for example TTBRx_EL1.CnP is permitted > to be cached in a TLB). > > CHeers, > > Will > _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
