Hi Alex, > From: Alex Williamson <alex.williamson@xxxxxxxxxx> > On Mon, 3 May 2021 13:59:43 +0000 > Vikram Sethi <vsethi@xxxxxxxxxx> wrote: > > > From: Mark Kettenis <mark.kettenis@xxxxxxxxx> > > > > From: Marc Zyngier <maz@xxxxxxxxxx> > > > > snip > > > > If, by enumerating the properties of Prefetchable, you can show > > > > that they are a strict superset of Normal_NC, I'm on board. I > > > > haven't seen such an enumeration so far. > > > > > > snip > > > > Right, so we have made a small step in the direction of mapping > > > > "prefetchable" onto "Normal_NC", thanks for that. What about all > > > > the other properties (unaligned accesses, ordering, gathering)? > > > > > Regarding gathering/write combining, that is also allowed to > > prefetchable per PCI spec > > As others have stated, gather/write combining itself is not well defined. > > > From 1.3.2.2 of 5/0 base spec: > > A PCI Express Endpoint requesting memory resources through a BAR must > > set the BAR's Prefetchable bit unless the range contains locations > > with read side-effects or locations in which the Function does not tolerate > write merging. > > "write merging" This is a very specific thing, per PCI 3.0, 3.2.6: > > Byte Merging – occurs when a sequence of individual memory writes > (bytes or words) are merged into a single DWORD. > > The semantics suggest quadword support in addition to dword, but don't > require it. Writes to bytes within a dword can be merged, but duplicate > writes cannot. > > It seems like an extremely liberal application to suggest that this one write > semantic encompasses full write combining semantics, which itself is not > clearly defined. > Talking to our PCIe SIG representative, PCIe switches are not allowed do any of the byte Merging/combining etc as defined in the PCI spec, and per a rather poorly worded Implementation note in the spec says that no known PCIe Host Briddges/Root ports do it either. So for PCIe we don't think believe there is any byte merging that happens in the PCIe fabric so it's really a matter of what happens in the CPU core and interconnect before it gets to the PCIe hierarchy. Stepping back from this patchset, do you agree that it is desirable to support Write combining as understood by ioremap_wc to work in all ISA guests including ARMv8? You note that x86 virtualization doesn't have this issue, but KVM-ARM does because KVM maps all device BARs as Device Memory type nGnRE which doesn't allow ioremap_wc from within the guest to get the actual semantics desired. Marc and others have suggested that userspace should provide the hints. But the question is how would qemu vfio do this either? We would be stuck in the same arguments as here, as to what is the correct way to determine the desired attributes for a given BAR such that eventually when a driver in the guest asks for ioremap_wc it actually has a chance of working in the guest, in all ISAs. Do you have any suggestions on how to make progress here? A device specific list of which BARs are OK to allow ioremap_wc for seems terrible and I'm not sure if a commandline qemu option is any better. Is the user of device assignment/sysadmin supposed to know which BAR of which device is OK to allow ioremap_wc for? Will/Catalin, perhaps you could explain your thought process on why you chose Normal NC for ioremap_wc on the armv8 linux port instead of Device GRE or other Device Gxx. Thanks, Vikram _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
