On 2021-04-28 11:18, Alex Bennée wrote:
A few of the its-trigger tests rely on IMPDEF behaviour where caches
aren't flushed before invall events. However TCG emulation doesn't
model any invall behaviour and as we can't probe for it we need to be
told. Split the test into a KVM and TCG variant and skip the invall
tests when under TCG.
Signed-off-by: Alex Bennée <alex.bennee@xxxxxxxxxx>
Cc: Shashi Mallela <shashi.mallela@xxxxxxxxxx>
---
arm/gic.c | 60 +++++++++++++++++++++++++++--------------------
arm/unittests.cfg | 11 ++++++++-
2 files changed, 45 insertions(+), 26 deletions(-)
diff --git a/arm/gic.c b/arm/gic.c
index 98135ef..96a329d 100644
--- a/arm/gic.c
+++ b/arm/gic.c
@@ -36,6 +36,7 @@ static struct gic *gic;
static int acked[NR_CPUS], spurious[NR_CPUS];
static int irq_sender[NR_CPUS], irq_number[NR_CPUS];
static cpumask_t ready;
+static bool under_tcg;
static void nr_cpu_check(int nr)
{
@@ -734,32 +735,38 @@ static void test_its_trigger(void)
/*
* re-enable the LPI but willingly do not call invall
* so the change in config is not taken into account.
- * The LPI should not hit
+ * The LPI should not hit. This does however depend on
+ * implementation defined behaviour - under QEMU TCG emulation
+ * it can quite correctly process the event directly.
It looks to me that you are using an IMPDEF behaviour of *TCG*
here. The programming model mandates that there is an invalidation
if you change the configuration of the LPI.
M.
--
Jazz is not dead. It just smells funny...
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