On Wed, Mar 03, 2021 at 04:45:05PM +0000, Marc Zyngier wrote: > It recently became apparent that the ARMv8 architecture has interesting > rules regarding attributes being used when fetching instructions > if the MMU is off at Stage-1. > > In this situation, the CPU is allowed to fetch from the PoC and > allocate into the I-cache (unless the memory is mapped with > the XN attribute at Stage-2). > > If we transpose this to vcpus sharing a single physical CPU, > it is possible for a vcpu running with its MMU off to influence > another vcpu running with its MMU on, as the latter is expected to > fetch from the PoU (and self-patching code doesn't flush below that > level). > > In order to solve this, reuse the vcpu-private TLB invalidation > code to apply the same policy to the I-cache, nuking it every time > the vcpu runs on a physical CPU that ran another vcpu of the same > VM in the past. > > This involve renaming __kvm_tlb_flush_local_vmid() to > __kvm_flush_cpu_context(), and inserting a local i-cache invalidation > there. > > Cc: stable@xxxxxxxxxxxxxxx > Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx> > --- > arch/arm64/include/asm/kvm_asm.h | 4 ++-- > arch/arm64/kvm/arm.c | 7 ++++++- > arch/arm64/kvm/hyp/nvhe/hyp-main.c | 6 +++--- > arch/arm64/kvm/hyp/nvhe/tlb.c | 3 ++- > arch/arm64/kvm/hyp/vhe/tlb.c | 3 ++- > 5 files changed, 15 insertions(+), 8 deletions(-) Since the FWB discussion doesn't affect the correctness of this patch: Acked-by: Will Deacon <will@xxxxxxxxxx> Will _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
