Hi Quentin,
On 2021-01-08 13:14, Quentin Perret wrote:
Hi all,
This is the v2 of the series previously posted here:
https://lore.kernel.org/kvmarm/20201117181607.1761516-1-qperret@xxxxxxxxxx/
This basically allows us to wrap the host with a stage 2 when running in
nVHE, hence paving the way for protecting guest memory from the host in
the future (among other use-cases). For more details about the
motivation and the design angle taken here, I would recommend to have a
look at the cover letter of v1, and/or to watch these presentations at
LPC [1] and KVM forum 2020 [2].
We tested the pKVM changes pulled from here:
https://android-kvm.googlesource.com/linux qperret/host-stage2-v2
We were using a target with Arm architecture with FEAT_S2FWB, and found
that there is a bug in the patch.
It turned out that the Kernel checks for the extension, and sets up the
stage 2 translation so that it forces the host memory type to
write-through. However it seems that the code doesn't turn on the
feature in the HCR_EL2 register.
We were able to fix the issue by applying the following patch:
diff --git a/arch/arm64/kvm/hyp/nvhe/mem_protect.c
b/arch/arm64/kvm/hyp/nvhe/mem_protect.c
index 0cd3eb178f3b..e8521a072ea6 100644
--- a/arch/arm64/kvm/hyp/nvhe/mem_protect.c
+++ b/arch/arm64/kvm/hyp/nvhe/mem_protect.c
@@ -105,6 +105,8 @@ int kvm_host_prepare_stage2(void *mem_pgt_pool, void
*dev_pgt_pool)
params->vttbr = kvm_get_vttbr(mmu);
params->vtcr = host_kvm.arch.vtcr;
params->hcr_el2 |= HCR_VM;
+ if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
+ params->hcr_el2 |= HCR_FWB;
__flush_dcache_area(params, sizeof(*params));
}
Best regards,
Mate Toth-Pal
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