On 2021-02-04 09:34, Will Deacon wrote:
On Thu, Feb 04, 2021 at 09:30:08AM +0000, Marc Zyngier wrote:
[...]
I think the following patch addresses the above issue, which I'll
squash
with the original patch. Please shout if I missed anything.
Thanks,
M.
diff --git a/arch/arm64/kernel/hyp-stub.S
b/arch/arm64/kernel/hyp-stub.S
index aa7e8d592295..3e08dcc924b5 100644
--- a/arch/arm64/kernel/hyp-stub.S
+++ b/arch/arm64/kernel/hyp-stub.S
@@ -115,29 +115,9 @@ SYM_CODE_START_LOCAL(mutate_to_vhe)
mrs_s x0, SYS_VBAR_EL12
msr vbar_el1, x0
- // Fixup SPE configuration, if supported...
- mrs x1, id_aa64dfr0_el1
- ubfx x1, x1, #ID_AA64DFR0_PMSVER_SHIFT, #4
- mov x2, xzr
- cbz x1, skip_spe
-
- // ... and not owned by EL3
- mrs_s x0, SYS_PMBIDR_EL1
- and x0, x0, #(1 << SYS_PMBIDR_EL1_P_SHIFT)
- cbnz x0, skip_spe
-
- // Let the SPE driver in control of the sampling
- mrs_s x0, SYS_PMSCR_EL1
- bic x0, x0, #(1 << SYS_PMSCR_EL2_PCT_SHIFT)
- bic x0, x0, #(1 << SYS_PMSCR_EL2_PA_SHIFT)
- msr_s SYS_PMSCR_EL1, x0
- mov x2, #MDCR_EL2_TPMS
-
-skip_spe:
- // For VHE, use EL2 translation and disable access from EL1
+ // Use EL2 translations for SPE and disable access from EL1
mrs x0, mdcr_el2
bic x0, x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT)
- orr x0, x0, x2
msr mdcr_el2, x0
Looks a tonne better, thanks! Be nice if somebody could test it for us.
SPE-equipped machines are the silicon equivalent of hen's teeth...
Alex, any chance you could give this a go?
M.
--
Jazz is not dead. It just smells funny...
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