Hi,
On 1/29/21 5:36 PM, Alexandru Elisei wrote:
> The GICv3 driver executes a DSB barrier before sending an IPI, which
> ensures that memory accesses have completed. This removes the need to
> enforce ordering with respect to stats_reset() in the IPI handler.
>
> For GICv2, the same barrier is executed by readl() after the MMIO read.
> Together with the wmb() barrier from writel() when triggering the IPI,
> this ensures that the expected memory ordering is respected.
>
> Signed-off-by: Alexandru Elisei <alexandru.elisei@xxxxxxx>
Reviewed-by: Eric Auger <eric.auger@xxxxxxxxxx>
Eric
> ---
> arm/gic.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/arm/gic.c b/arm/gic.c
> index 8bb804abf34d..db1417ae1ca1 100644
> --- a/arm/gic.c
> +++ b/arm/gic.c
> @@ -59,7 +59,6 @@ static void stats_reset(void)
> bad_sender[i] = -1;
> bad_irq[i] = -1;
> }
> - smp_wmb();
> }
>
> static void check_acked(const char *testname, cpumask_t *mask)
> @@ -149,7 +148,6 @@ static void ipi_handler(struct pt_regs *regs __unused)
>
> if (irqnr != GICC_INT_SPURIOUS) {
> gic_write_eoir(irqstat);
> - smp_rmb(); /* pairs with wmb in stats_reset */
> ++acked[smp_processor_id()];
> check_ipi_sender(irqstat);
> check_irqnr(irqnr);
>
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