On Mon, Jan 18, 2021 at 09:45:14AM +0000, Marc Zyngier wrote: > The arm64 kernel has long be able to use more than 39bit VAs. > Since day one, actually. Let's rewrite the offending comment. > > Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx> > --- > arch/arm64/mm/proc.S | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S > index 1f7ee8c8b7b8..ece785477bdc 100644 > --- a/arch/arm64/mm/proc.S > +++ b/arch/arm64/mm/proc.S > @@ -464,8 +464,8 @@ SYM_FUNC_START(__cpu_setup) > #endif > msr mair_el1, x5 > /* > - * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for > - * both user and kernel. > + * Set/prepare TCR and TTBR. TCR_EL1.T1SZ gets further > + * adjusted if the kernel is compiled with 52bit VA support. I think both T0SZ and T1SZ get updated based on a mismatch between the kernel configuration and the hardware support. Anyway, I'm not asking for a detailed comment here, so: Acked-by: Catalin Marinas <catalin.marinas@xxxxxxx> _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
