On 2020-11-03 18:29, James Morse wrote:
Hi Marc,
On 02/11/2020 19:16, Marc Zyngier wrote:
Similarly to what has been done on the cp15 front, repaint the
debug registers to use their AArch64 counterparts. This results
in some simplification as we can remove the 32bit-specific
accessors.
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 137818793a4a..c41e7ca60c8c 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -361,26 +361,30 @@ static bool trap_debug_regs(struct kvm_vcpu
*vcpu,
-#define DBGBXVR(n) \
- { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n }
+#define DBG_BCR_BVR_WCR_WVR(n) \
+ /* DBGBVRn */ \
+ { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n
}, \
Just to check I understand what is going on here: This BVR AA32(LO) is
needed because the
dbg_bvr array is shared with the DBGBXVR registers...
+ /* DBGBCRn */ \
+ { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n
}, \
+ /* DBGWVRn */ \
+ { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n
}, \
+ /* DBGWCRn */ \
+ { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
... these don't have an alias, but its harmless.
This is a bug-for-bug translation of the original code. I guess I'll
drop
that altogether.
[...]
@@ -1931,7 +1896,9 @@ static const struct sys_reg_desc cp15_regs[] = {
/* DFSR */
{ Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1
},
{ Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL,
IFSR32_EL2 },
+ /* ADFSR */
{ Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1
},
+ /* AIFSR */
{ Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1
},
/* DFAR */
{ AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL,
FAR_EL1 },
I guess these were meant for the previous patch.
Yup, I'll move that.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
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