On Thu, Oct 29, 2020 at 5:04 AM Catalin Marinas <catalin.marinas@xxxxxxx> wrote: > > On Wed, Oct 28, 2020 at 01:28:39PM -0500, Rob Herring wrote: > > On Cortex-A77 r0p0 and r1p0, a sequence of a non-cacheable or device load > > and a store exclusive or PAR_EL1 read can cause a deadlock. > > > > The workaround requires a DMB SY before and after a PAR_EL1 register > > read. In addition, it's possible an interrupt (doing a device read) or > > KVM guest exit could be taken between the DMB and PAR read, so we > > also need a DMB before returning from interrupt and before returning to > > a guest. > > > > A deadlock is still possible with the workaround as KVM guests must also > > have the workaround. IOW, a malicious guest can deadlock an affected > > systems. > > > > This workaround also depends on a firmware counterpart to enable the h/w > > to insert DMB SY after load and store exclusive instructions. See the > > errata document SDEN-1152370 v10 [1] for more information. > > > > [1] https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf > > > > Cc: Catalin Marinas <catalin.marinas@xxxxxxx> > > Cc: James Morse <james.morse@xxxxxxx> > > Cc: Suzuki K Poulose <suzuki.poulose@xxxxxxx> > > Cc: Will Deacon <will@xxxxxxxxxx> > > Cc: Julien Thierry <julien.thierry.kdev@xxxxxxxxx> > > Cc: kvmarm@xxxxxxxxxxxxxxxxxxxxx > > Acked-by: Marc Zyngier <maz@xxxxxxxxxx> > > Signed-off-by: Rob Herring <robh@xxxxxxxxxx> > > I thought I reviewed the v6 already and that's just a rebase. Here it is > again: > > Reviewed-by: Catalin Marinas <catalin.marinas@xxxxxxx> You did. Sorry, I forgot to add it. Rob _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
