Hi Andrew,
On 2020-07-30 23:31, Andrew Scull wrote:
On Thu, Jul 30, 2020 at 04:18:23PM +0100, Andrew Scull wrote:
The ESB at the start of the vectors causes any SErrors to be consumed
to
DISR_EL1. If the exception came from the host and the ESB caught an
SError, it would not be noticed until a guest exits and DISR_EL1 is
checked. Further, the SError would be attributed to the guest and not
the host.
To avoid these problems, use a different exception vector for the host
that does not use an ESB but instead leaves any host SError pending. A
guest will not be entered if an SError is pending so it will always be
the host that will receive and handle it.
Thinking further, I'm not sure this actually solves all of the problem.
It does prevent hyp from causing a host SError to be consumed but,
IIUC,
there could be an SError already deferred by the host and logged in
DISR_EL1 that hyp would not preserve if a guest is run.
I think the host's DISR_EL1 would need to be saved and restored in the
vcpu context switch which, from a cursory read of the ARM, is possible
without having to virtualize SErrors for the host.
The question is what do you if you have something pending in DISR_EL1
at the point where you enter EL2? Context switching it is not going to
help. One problem is that you'd need to do an ESB, corrupting DISR_EL1,
before any memory access (I'm assuming you can get traps where all
registers are live). I can't see how we square this circle.
Furthermore, assuming you find a way to do it, what do you do with it?
(a) Either there was something pending already and it is still pending,
(b) Or there was nothing pending and you now have an error that you
don't know how to report (the host EL1 never issued an ESB)
We could just error out on hypercalls if DISR_EL1 is non-zero, but
I don't see how we do that for traps, as it would just confuse the host
EL1.
M.
--
Jazz is not dead. It just smells funny...
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