On Mon, May 04, 2020 at 10:48:58AM +0100, Andrew Scull wrote: > Errata 1165522, 1319367 and 1530923 each allow TLB entries to be > allocated as a result of a speculative AT instruction. In order to > avoid mandating VHE on certain affected CPUs, apply the workaround to > both the nVHE and the VHE case for all affected CPUs. > > Signed-off-by: Andrew Scull <ascull@xxxxxxxxxx> > CC: Marc Zyngier <maz@xxxxxxxxxx> > CC: James Morse <james.morse@xxxxxxx> > CC: Suzuki K Poulose <suzuki.poulose@xxxxxxx> > CC: Will Deacon <will@xxxxxxxxxx> > CC: Steven Price <steven.price@xxxxxxx> > --- > From v2 <20200422161346.67325-1-ascull@xxxxxxxxxx>: > - const_cap -> final_cap merge correction > - based on 5.7 rc4 > --- > arch/arm64/Kconfig | 39 ++++++++++++++----------------- > arch/arm64/include/asm/cpucaps.h | 15 ++++++------ > arch/arm64/include/asm/kvm_host.h | 4 ---- > arch/arm64/include/asm/kvm_hyp.h | 2 +- > arch/arm64/kernel/cpu_errata.c | 25 +++++++++----------- > arch/arm64/kvm/hyp/switch.c | 6 ++--- > arch/arm64/kvm/hyp/sysreg-sr.c | 6 +++-- > arch/arm64/kvm/hyp/tlb.c | 11 +++++---- > 8 files changed, 50 insertions(+), 58 deletions(-) Acked-by: Will Deacon <will@xxxxxxxxxx> We'll probably run into some trivial conflicts with the arm64 tree, but I'm happy to put this on a branch if it helps. Marc? Will _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
