On 02/14/2020 09:28 PM, Peter Maydell wrote: > On Fri, 14 Feb 2020 at 04:23, Anshuman Khandual > <anshuman.khandual@xxxxxxx> wrote: >> >> >> >> On 01/28/2020 06:09 PM, Anshuman Khandual wrote: >>> This series is primarily motivated from an adhoc list from Mark Rutland >>> during our ID_ISAR6 discussion [1]. Besides, it also includes a patch >>> which does macro replacement for various open bits shift encodings in >>> various CPU ID registers. This series is based on linux-next 20200124. >>> >>> [1] https://patchwork.kernel.org/patch/11287805/ >>> >>> Is there anything else apart from these changes which can be accommodated >>> in this series, please do let me know. Thank you. >> >> Just a gentle ping. Any updates, does this series looks okay ? Is there >> anything else related to CPU ID register feature bits, which can be added >> up here. FWIW, the series still applies on v5.6-rc1. Sorry for the delay in response, was distracted on some other patches. > > I just ran into some "32-bit KVM doesn't expose all the ID > registers to userspace via the ONE_REG API" issues today. > I don't know if they'd be reasonable as something to include > in this patchset or if they're unrelated. IMHO, they are bit unrelated. > > Anyway, missing stuff I have noticed specifically: > * MVFR2 > * ID_MMFR4 > * ID_ISAR6 > > More generally I would have expected all these 32-bit registers > to exist and read-as-zero for the purpose of the ONE_REG APIs, > because that's what the architecture says is supposed to happen > and it means we have compatibility and QEMU doesn't gradually > build up lots of "kernel doesn't support this yet" conditionals... > I think we get this right for 64-bit KVM, but can we do it for > 32-bit as well? I am not very familiar with 32-bit KVM but will definitely keep these suggestions noted for later, also try and accommodate if possible. > thanks > -- PMM > _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
