On 2020-03-02 09:21, Zenghui Yu wrote:
In GICv4.1, we emulate a guest-issued INVALL command by a direct write
to GICR_INVALLR. Before we finish the emulation and go back to guest,
let's make sure the physical invalidate operation is actually completed
and no stale data will be left in redistributor. Per the specification,
this can be achieved by polling the GICR_SYNCR.Busy bit (to zero).
Signed-off-by: Zenghui Yu <yuzenghui@xxxxxxxxxx>
---
drivers/irqchip/irq-gic-v3-its.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/irqchip/irq-gic-v3-its.c
b/drivers/irqchip/irq-gic-v3-its.c
index 83b1186ffcad..fc8c2970cee4 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -3784,6 +3784,8 @@ static void its_vpe_4_1_invall(struct its_vpe
*vpe)
/* Target the redistributor this vPE is currently known on */
rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
gic_write_lpir(val, rdbase + GICR_INVALLR);
+
+ wait_for_syncr(rdbase);
}
static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void
*vcpu_info)
Yup, well spotted. I'll add that to the series.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
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