While writing new PMUv3 event counter KVM unit tests I found 3 things that do not seem to comply with the specification and at least need to be confirmed. Two are related to SW_INCR implementation: no check of the PMCR.E bit, no support of 64b (CHAIN). From the spec, I do not understand the SW_INCR behaves differently from other events but I may be wrong. The last minor thing is about the PMEVTYPER read-only bits. On Seattle we have an 8.0 implementation which I understand is supposed to implement only 10-bit evtCount field which is not enforced. Best Regards Eric This series can be found at: https://github.com/eauger/qemu/tree/v5.4-pmu-kut-fixes-v1 Eric Auger (3): KVM: arm64: pmu: Don't increment SW_INCR if PMCR.E is unset KVM: arm64: pmu: Fix chained SW_INCR counters KVM: arm64: pmu: Enforce PMEVTYPER evtCount size arch/arm64/include/asm/perf_event.h | 5 ++++- arch/arm64/include/asm/sysreg.h | 5 +++++ arch/arm64/kernel/perf_event.c | 2 +- arch/arm64/kvm/sys_regs.c | 14 ++++++++++---- virt/kvm/arm/pmu.c | 19 ++++++++++++++++++- 5 files changed, 38 insertions(+), 7 deletions(-) -- 2.20.1 _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
