When configuring an interrupt as Group 0, we can ask the GIC to deliver
them as a FIQ. For this we need a separate exception handler.
Provide this to be used later.
Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx>
---
arm/gic.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arm/gic.c b/arm/gic.c
index c68b5b5..6756850 100644
--- a/arm/gic.c
+++ b/arm/gic.c
@@ -178,6 +178,30 @@ static void irq_handler(struct pt_regs *regs __unused)
smp_wmb(); /* pairs with rmb in check_acked */
}
+static inline void fiq_handler(struct pt_regs *regs __unused)
+{
+ u32 irqstat = gic_read_iar(0);
+ u32 irqnr = gic_iar_irqnr(irqstat);
+
+ if (irqnr == GICC_INT_SPURIOUS) {
+ ++spurious[smp_processor_id()];
+ smp_wmb();
+ return;
+ }
+
+ gic_write_eoir(irqstat, 0);
+
+ smp_rmb(); /* pairs with wmb in stats_reset */
+ ++acked[smp_processor_id()];
+ if (irqnr < GIC_NR_PRIVATE_IRQS) {
+ check_ipi_sender(irqstat);
+ check_irqnr(irqnr, IPI_IRQ);
+ } else {
+ check_irqnr(irqnr, SPI_IRQ);
+ }
+ smp_wmb(); /* pairs with rmb in check_acked */
+}
+
static void gicv2_ipi_send_self(void)
{
writel(2 << 24 | IPI_IRQ, gicv2_dist_base() + GICD_SGIR);
--
2.17.1
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