Hi Marc, On 25/09/2019 12:19, Marc Zyngier wrote: > Now that everything is in place, let's get the ball rolling > by allowing the corresponding config option to be selected. > Also add the required information to silicon_arrata.rst. > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 3adcec05b1f6..c50cd4f83bc4 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -523,6 +523,16 @@ config ARM64_ERRATUM_1286807 > invalidated has been observed by other observers. The > workaround repeats the TLBI+DSB operation. > > +config ARM64_ERRATUM_1319367 > + bool "Cortex-A57/A72: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" > + default y > + help > + This option adds work arounds for ARM Cortex-A57 erratum 1319537 > + and A72 erratum 1319367 > + > + Cortex-A57 and A72 cores could end-up with corrupted TLBs by > + speculating an AT instruction during a guest context switch. > + > If unsure, say Y. > > config ARM64_ERRATUM_1463225 > Nit: You pinched someone elses "If unsure, say Y."! Thanks, James _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
