On 27/08/2019 18:06, James Morse wrote:
> Since commit 2f6ea23f63cca ("arm64: KVM: Avoid marking pages as XN in
> Stage-2 if CTR_EL0.DIC is set"), KVM has stopped marking normal memory
> as execute-never at stage2 when the system supports D->I Coherency at
> the PoU. This avoids KVM taking a trap when the page is first executed,
> in order to clean it to PoU.
>
> The patch that added this change also wrapped PAGE_S2_DEVICE mappings
> up in this too. The upshot is, if your CPU caches support DIC ...
> you can execute devices.
Amazing. And we all missed that, while it should have been obvious. Oh
well...
>
> Revert the PAGE_S2_DEVICE change so PTE_S2_XN is always used
> directly.
>
> Fixes: 2f6ea23f63cca ("arm64: KVM: Avoid marking pages as XN in Stage-2 if CTR_EL0.DIC is set")
> Signed-off-by: James Morse <james.morse@xxxxxxx>
> ---
> arch/arm64/include/asm/pgtable-prot.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h
> index 92d2e9f28f28..9a21b84536f2 100644
> --- a/arch/arm64/include/asm/pgtable-prot.h
> +++ b/arch/arm64/include/asm/pgtable-prot.h
> @@ -77,7 +77,7 @@
> })
>
> #define PAGE_S2 __pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(NORMAL) | PTE_S2_RDONLY | PAGE_S2_XN)
> -#define PAGE_S2_DEVICE __pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(DEVICE_nGnRE) | PTE_S2_RDONLY | PAGE_S2_XN)
> +#define PAGE_S2_DEVICE __pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_S2_XN)
>
> #define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
> #define PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
>
Applied to -next.
Thanks,
M.
--
Jazz is not dead, it just smells funny...
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