Hi Marc,
On 7/25/19 5:35 PM, Marc Zyngier wrote:
> From: Marc Zyngier <marc.zyngier@xxxxxxx>
>
> If a vcpu disables LPIs at its redistributor level, we need to make sure
> we won't pend more interrupts. For this, we need to invalidate the LPI
> translation cache.
>
> Signed-off-by: Marc Zyngier <marc.zyngier@xxxxxxx>
Reviewed-by: Eric Auger <eric.auger@xxxxxxxxxx>
Eric
> ---
> virt/kvm/arm/vgic/vgic-mmio-v3.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/virt/kvm/arm/vgic/vgic-mmio-v3.c b/virt/kvm/arm/vgic/vgic-mmio-v3.c
> index 936962abc38d..cb60da48810d 100644
> --- a/virt/kvm/arm/vgic/vgic-mmio-v3.c
> +++ b/virt/kvm/arm/vgic/vgic-mmio-v3.c
> @@ -192,8 +192,10 @@ static void vgic_mmio_write_v3r_ctlr(struct kvm_vcpu *vcpu,
>
> vgic_cpu->lpis_enabled = val & GICR_CTLR_ENABLE_LPIS;
>
> - if (was_enabled && !vgic_cpu->lpis_enabled)
> + if (was_enabled && !vgic_cpu->lpis_enabled) {
> vgic_flush_pending_lpis(vcpu);
> + vgic_its_invalidate_cache(vcpu->kvm);
> + }
>
> if (!was_enabled && vgic_cpu->lpis_enabled)
> vgic_enable_lpis(vcpu);
>
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