Hi Marc,
On 6/6/19 6:54 PM, Marc Zyngier wrote:
> Add the basic data structure that expresses an MSI to LPI
> translation as well as the allocation/release hooks.
>
> THe size of the cache is arbitrarily defined as 4*nr_vcpus.
>
> Signed-off-by: Marc Zyngier <marc.zyngier@xxxxxxx>
> ---
> include/kvm/arm_vgic.h | 10 ++++++++++
> virt/kvm/arm/vgic/vgic-init.c | 34 ++++++++++++++++++++++++++++++++++
> virt/kvm/arm/vgic/vgic-its.c | 2 ++
> virt/kvm/arm/vgic/vgic.h | 3 +++
> 4 files changed, 49 insertions(+)
>
> diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h
> index c36c86f1ec9a..5a0d6b07c5ef 100644
> --- a/include/kvm/arm_vgic.h
> +++ b/include/kvm/arm_vgic.h
> @@ -173,6 +173,14 @@ struct vgic_io_device {
> struct kvm_io_device dev;
> };
>
> +struct vgic_translation_cache_entry {
> + struct list_head entry;
> + phys_addr_t db;
it is not obvious to me why you do need the db field? Isn't the LPI
uniquely identfiied by the devid and eventid. If I recall correctly
theorically the architecture allows to handle LPIs even without ITS.
> + u32 devid;
> + u32 eventid;
> + struct vgic_irq *irq;
> +};
> +
> struct vgic_its {
> /* The base address of the ITS control register frame */
> gpa_t vgic_its_base;
> @@ -260,6 +268,8 @@ struct vgic_dist {
> struct list_head lpi_list_head;
> int lpi_list_count;
>
> + struct list_head lpi_translation_cache;
> +
> /* used by vgic-debug */
> struct vgic_state_iter *iter;
>
> diff --git a/virt/kvm/arm/vgic/vgic-init.c b/virt/kvm/arm/vgic/vgic-init.c
> index 3bdb31eaed64..25ae25694a28 100644
> --- a/virt/kvm/arm/vgic/vgic-init.c
> +++ b/virt/kvm/arm/vgic/vgic-init.c
> @@ -64,6 +64,7 @@ void kvm_vgic_early_init(struct kvm *kvm)
> struct vgic_dist *dist = &kvm->arch.vgic;
>
> INIT_LIST_HEAD(&dist->lpi_list_head);
> + INIT_LIST_HEAD(&dist->lpi_translation_cache);
> raw_spin_lock_init(&dist->lpi_list_lock);
> }
>
> @@ -260,6 +261,27 @@ static void kvm_vgic_vcpu_enable(struct kvm_vcpu *vcpu)
> vgic_v3_enable(vcpu);
> }
>
> +void vgic_lpi_translation_cache_init(struct kvm *kvm)
> +{
> + struct vgic_dist *dist = &kvm->arch.vgic;
> + int i;
> +
> + if (!list_empty(&dist->lpi_translation_cache))
> + return;
> +
> + for (i = 0; i < LPI_CACHE_SIZE(kvm); i++) {
> + struct vgic_translation_cache_entry *cte;
> +
> + /* An allocation failure is not fatal */
> + cte = kzalloc(sizeof(*cte), GFP_KERNEL);
> + if (WARN_ON(!cte))
> + break;
> +
> + INIT_LIST_HEAD(&cte->entry);
> + list_add(&cte->entry, &dist->lpi_translation_cache);
> + }
> +}
> +
> /*
> * vgic_init: allocates and initializes dist and vcpu data structures
> * depending on two dimensioning parameters:
> @@ -305,6 +327,7 @@ int vgic_init(struct kvm *kvm)
> }
>
> if (vgic_has_its(kvm)) {
> + vgic_lpi_translation_cache_init(kvm);
> ret = vgic_v4_init(kvm);
> if (ret)
> goto out;
> @@ -346,6 +369,17 @@ static void kvm_vgic_dist_destroy(struct kvm *kvm)
> INIT_LIST_HEAD(&dist->rd_regions);
> }
>
> + if (vgic_has_its(kvm)) {
> + struct vgic_translation_cache_entry *cte, *tmp;
> +
> + list_for_each_entry_safe(cte, tmp,
> + &dist->lpi_translation_cache, entry) {
> + list_del(&cte->entry);
> + kfree(cte);
> + }
> + INIT_LIST_HEAD(&dist->lpi_translation_cache);
> + }
> +
> if (vgic_supports_direct_msis(kvm))
> vgic_v4_teardown(kvm);
> }
> diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgic/vgic-its.c
> index 44ceaccb18cf..5758504fd934 100644
> --- a/virt/kvm/arm/vgic/vgic-its.c
> +++ b/virt/kvm/arm/vgic/vgic-its.c
> @@ -1696,6 +1696,8 @@ static int vgic_its_create(struct kvm_device *dev, u32 type)
> kfree(its);
> return ret;
> }
> +
> + vgic_lpi_translation_cache_init(dev->kvm);
> }
>
> mutex_init(&its->its_lock);
> diff --git a/virt/kvm/arm/vgic/vgic.h b/virt/kvm/arm/vgic/vgic.h
> index abeeffabc456..a58e1b263dca 100644
> --- a/virt/kvm/arm/vgic/vgic.h
> +++ b/virt/kvm/arm/vgic/vgic.h
> @@ -316,6 +316,9 @@ int vgic_copy_lpi_list(struct kvm *kvm, struct kvm_vcpu *vcpu, u32 **intid_ptr);
> int vgic_its_resolve_lpi(struct kvm *kvm, struct vgic_its *its,
> u32 devid, u32 eventid, struct vgic_irq **irq);
> struct vgic_its *vgic_msi_to_its(struct kvm *kvm, struct kvm_msi *msi);
> +void vgic_lpi_translation_cache_init(struct kvm *kvm);
> +
> +#define LPI_CACHE_SIZE(kvm) (atomic_read(&(kvm)->online_vcpus) * 4)
Couldn't the cache be a function of the number of allocated lpis. We
could realloc the list accordingly. I miss why it is rather dependent on
the number of vcpus and not on the number of assigned devices/MSIs?
Thanks
Eric
>
> bool vgic_supports_direct_msis(struct kvm *kvm);
> int vgic_v4_init(struct kvm *kvm);
>
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