Currently, we support the following page sizes at stage2:
PTE PMD PUD
----- ----- -----
4K granule: 4K 2M 1G
16K granule: 16K 32M
64K granule: 64K 512M
And we have Contiguous bit[52] in stage2 VMSAv8-64 block and page
descriptors. As ARM ARM said, when the value of the Contiguous bit
is 1, it indicates that the entry is one of a number of adjacent
translation table entries that point to a contiguous output address
range.
This series add support for contiguous PTE/PMD hugepages at stage2
and then we can create huge mappings with following additional
sizes:
CONT PTE CONT PMD
-------- --------
4K granule: 64K 32M
16K granule: 2M 1G
64K granule: 2M 16G
These patches are based on v5.1.0-rc7 and have been tested on
Taishan 2280 server (D05) with 4K and 64K granule.
Any comments will be appreciated, thanks!
Zenghui Yu (5):
KVM: arm/arm64: Introduce helpers for page table enties with
contiguous bit
KVM: arm/arm64: Re-factor building the stage2 page table entries
KVM: arm/arm64: Support dirty page tracking for contiguous hugepages
KVM: arm/arm64: Add support for creating PTE contiguous hugepages at
stage2
KVM: arm/arm64: Add support for creating PMD contiguous hugepages at
stage2
arch/arm/include/asm/kvm_mmu.h | 22 +++
arch/arm/include/asm/pgtable-hwdef.h | 8 +
arch/arm64/include/asm/kvm_mmu.h | 20 +++
virt/kvm/arm/mmu.c | 299 ++++++++++++++++++++++++++++++-----
4 files changed, 312 insertions(+), 37 deletions(-)
--
1.8.3.1
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