On Mon, 4 Feb 2019 16:53:33 +0000 Andrew Murray <andrew.murray at arm.com> wrote: > ARMv8 provides support for chained PMU counters, where an event type > of 0x001E is set for odd-numbered counters, the event counter will > increment by one for each overflow of the preceding even-numbered > counter. Let's emulate this in KVM by creating a 64 bit perf counter > when a user chains two emulated counters together. > > Testing has been performed by hard-coding hwc->sample_period in > __hw_perf_event_init (arm_pmu.c) to a small value, this results in > regular overflows (for non sampling events). The following command > was then used to measure chained and non-chained instruction cycles: > > perf stat -e armv8_pmuv3/long=1,inst_retired/u \ > -e armv8_pmuv3/long=0,inst_retired/u dd if=/dev/zero bs=1M \ > count=10 | gzip > /dev/null > > The reported values were identical (and for non-chained was in the > same ballpark when running on a kernel without this patchset). Debug > was added to verify that the guest received overflow interrupts for > the chain counter. Hi Andrew, We're getting quite close to the merge window, and I need to wrap up the pull request pretty soon. If you want this to make it into 5.1, you'll have to respin it pretty quickly (right now, basically...), addressing the comments Suzuki and Julien raised. Thanks, M. -- Without deviation from the norm, progress is not possible.
