While looking into whether we could report the cache geometry as 1 set and 1 way so that the ARM kernel doesn't stall for 13 seconds at boot, I noticed that we don't expose the sanitised version of CTR_EL0 to guests, so I fixed that first (#1) Since that gives us most of the groundwork for overriding the cache geometry, it is a fairly trivial change (#2) to clear the set/way fields in the CCSIDR register so that it describes 1 set and 1 way. Changes since v1: - fix incorrect mask value (#2) - make trapping conditional on whether either of the issues is being worked around, and it disabled otherwise - add Christoffer's ack Cc: Suzuki.Poulose@xxxxxxx Cc: marc.zyngier@xxxxxxx Cc: christoffer.dall@xxxxxxx Ard Biesheuvel (2): arm64: kvm: expose sanitised cache type register to guest arm64: kvm: describe data or unified caches as having 1 set and 1 way arch/arm64/include/asm/kvm_emulate.h | 4 ++ arch/arm64/include/asm/sysreg.h | 1 + arch/arm64/kvm/sys_regs.c | 74 +++++++++++++++++++- 3 files changed, 77 insertions(+), 2 deletions(-) -- 2.20.1 _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
