Hello! On 28/07/17 15:10, James Morse wrote: > Before we can enable Implicit ESB on exception level change, we need to > handle deferred SErrors that may appear on exception entry. Christoffer has pointed out on patch 16 that I've miss-understood IESB's behaviour: > The implicit form of Error Synchronization Barrier: [...] Has no effect on > DISR_EL1 Turns out the ARM-ARM psuedocode means subtly different things by 'ESB' and 'ErrorSynchronizationBarrier'. Patches 11->16 will need rethinking, but it looks like they can be simplified. Thanks, James _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
