Hello! > The only thing that is pure 64-bit is the MRS/MSR _instruction_ in > Aarch64, which always takes a x<nn> register. > So can you model the register size according to the spec and allow > 32-bit accesses from userland? I would like to complete the rework and respin v4, but this is, i guess, the only major issue left. Additionally, it impacts the API. So... In order to allow 32-bit accesses we would have to drop using ARM64_SYS_REG() for building attribute ID and introduce something own, like KVM_DEV_ARM_VGIC_REG(). It will have different bits layout (actually it will be missing 'arch' and 'size' field, and instead i will use KVM_DEV_ARM_VGIC_64BIT flag for length specification, the same as for redistributor. Will this be OK ? Kind regards, Pavel Fedin Expert Engineer Samsung Electronics Research center Russia _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
