On Tue, Mar 17, 2015 at 07:19:35PM +0000, Peter Maydell wrote:
> The AArch64 SPSR_EL1 register is architecturally mandated to
> be mapped to the AArch32 SPSR_svc register. This means its
> state should live in QEMU's env->banked_spsr[1] field.
> Correct the buggy regdef that put it in banked_spsr[0] instead.
>
> Signed-off-by: Peter Maydell <peter.maydell@xxxxxxxxxx>
> ---
> target-arm/helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 10886c5..d77c6de 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2438,7 +2438,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
> { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
> .type = ARM_CP_ALIAS,
> .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
> - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[0]) },
> + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[1]) },
> /* We rely on the access checks not allowing the guest to write to the
> * state field when SPSel indicates that it's being used as the stack
> * pointer.
> --
> 1.9.1
>
Don't you need to change aarch64_banked_spsr_index() accordingly?
-Christoffer
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