On Mon, Mar 02, 2015 at 04:57:22PM +0000, Baptiste Reynal wrote:
> This patch is a fix to "iommu/arm-smmu: add support for iova_to_phys
> through ATS1PR".
> According to ARM documentation, translation registers are optional even
> in SMMUv1, so ID0_S1TS needs to be checked to verify their presence.
>
> Signed-off-by: Baptiste Reynal <b.reynal@xxxxxxxxxxxxxxxxxxxxxx>
> ---
> drivers/iommu/arm-smmu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
> index fc13dd5..d4beca4 100644
> --- a/drivers/iommu/arm-smmu.c
> +++ b/drivers/iommu/arm-smmu.c
> @@ -1556,7 +1556,7 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
> return -ENODEV;
> }
>
> - if (smmu->version == 1 || (!(id & ID0_ATOSNS) && (id & ID0_S1TS))) {
> + if ((id & ID0_S1TS) && ((smmu->version == 1) || (id & ID0_ATOSNS))) {
> smmu->features |= ARM_SMMU_FEAT_TRANS_OPS;
> dev_notice(smmu->dev, "\taddress translation ops\n");
I'm not sure this is a complete fix. Shouldn't we also check that the domain
is a stage-1 domain in arm_smmu_iova_to_phys? (potential fixup below).
Will
--->8
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index fc13dd56953e..107163295cbc 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -1288,12 +1288,15 @@ static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
return 0;
spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
- if (smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_OPS)
+
+ if (smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_OPS &&
+ smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
ret = arm_smmu_iova_to_phys_hard(domain, iova);
- else
+ } else {
ret = ops->iova_to_phys(ops, iova);
- spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
+ }
+ spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
return ret;
}
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