On 24 February 2015 at 21:29, Richard W.M. Jones <rjones@xxxxxxxxxx> wrote: > On Tue, Feb 24, 2015 at 09:15:18PM +0900, Peter Maydell wrote: >> Complex insns are things like load-multiple (there's a complete >> list in the ARM ARM somewhere). Generally this indicates a guest >> bug because you really shouldn't be accessing devices with >> weird instructions like that (and you shouldn't be accessing >> unmapped memory at all). > > I'm not super-familiar with the aarch64 instruction set, but > according to qemu the instruction is: > > b8004403 str w3, [x0],#4 > > (in __copy_to_user). My interpretation is this is storing the > lower 32 bits of x3 into the storage pointed to by x0 (+ 4 bytes?) This syntax is post-indexed register writeback, ie "write lower 32 bits of x3 into the storage pointed to by x0, and then increment x0 by 4". > Is that one of the complicated ones? Yes. Writeback is one of the "complex" cases not handled by syndrome information alone. As Christoffer says, I'm not sure why we're getting a stage 2 abort on this __copy_to_user: the target of a __copy_to_user ought to either be guest RAM or something unmapped in stage 1, I would have thought... -- PMM _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
