On Wed, Jan 14, 2015 at 04:31:19PM +0000, Andre Przywara wrote: > With everything separated and prepared, we implement a model of a > GICv3 distributor and redistributors by using the existing framework > to provide handler functions for each register group. > > Currently we limit the emulation to a model enforcing a single > security state, with SRE==1 (forcing system register access) and > ARE==1 (allowing more than 8 VCPUs). > > We share some of the functions provided for GICv2 emulation, but take > the different ways of addressing (v)CPUs into account. > Save and restore is currently not implemented. > > Similar to the split-off of the GICv2 specific code, the new emulation > code goes into a new file (vgic-v3-emul.c). > > Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx> Drum roll.... Reviewed-by: Christoffer Dall <christoffer.dall@xxxxxxxxxx> _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
