Hi, Wondering what are plans for QEMU PCI, and associated kernel impl. supporting config space access cycles? I would like to enhance a QEMU device that has PCI support but depends on config space access registration and enumeration. Otherwise I would fall back to Device Tree/MMIO for the time being. It seems like ARM boards memory map config space (AXIv4) to various ranges. I've research a little and noticed AMBA5 CHI should support config space cycles. Hopefully I'm making sense here :) Thanks, - Mario _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
